Imperial College London


Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering



+44 (0)20 7594 8313w.luk Website




434Huxley BuildingSouth Kensington Campus






BibTex format

author = {Bsoul, AAM and Wilton, SJE and Tsoi, KH and Luk, W},
doi = {10.1109/TVLSI.2015.2393914},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
pages = {178--191},
title = {An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating},
url = {},
volume = {24},
year = {2015}

RIS format (EndNote, RefMan)

AB - Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time; the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application.
AU - Bsoul,AAM
AU - Wilton,SJE
AU - Tsoi,KH
AU - Luk,W
DO - 10.1109/TVLSI.2015.2393914
EP - 191
PY - 2015///
SN - 1063-8210
SP - 178
TI - An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating
T2 - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UR -
UR -
VL - 24
ER -