Imperial College London

Research Feature: Future 'bugs'

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Motherboard and CPU

Dr John Wickerson explains his latest research, helping detect possible bugs in computer chips - before they are even designed.

John WickersonDr Wickerson has been working with Dr Nathan Chong, Principal Researcher at Arm, and Tyler Sorensen, a PhD student in the Department of Computing.

WHAT HAVE YOU DISCOVERED?

Our project studies the interaction between two features of a modern computer, one called weak memory and one called transactional memory. Feature interactions are notoriously complicated, and therefore a fertile source of interesting bugs.

Using automated tools which analyse computer memory use, we discovered a problematic interaction between these two features in the Arm processor architecture, which could potentially cause bugs if programmers are not careful.

HOW DOES THIS WORK?

Weak memory is a feature that allows the computer chooses to perform instructions in a different order from that written by the programmer, for performance reasons. Transactional memory allows a programmer to group a sequence of instructions into a "transaction," which behaves as a single, uninterruptible instruction. While both of these independently useful features have been thoroughly studied in isolation, our work focuses on how they interact with each other.

We built mathematical models that capture weak memory and transactional memory, together, for a variety of chips including Intel’s x86 processors, IBM’s Power processors, and Arm's processors, and tested them against a range of real machines.

WHAT IS THE IMPACT OF THIS WORK?

Arm chips do not currently support transactional memory, but Arm researchers are investigating how transactional memory support could be added to future chips. We fed our model of Arm chips (tentatively extended with transactional memory) into an automated analysis tool that we developed, and the tool discovered a potential bug - that a well-studied lock implementation (a common programmer construct) using weak memory is incompatible with transactional memory.

This curious result is valuable because it reveals a problem in a chip that not only has not been manufactured yet, but has not even been designed yet!

If Arm decides to add transactional memory support to its future processors - we will have a model ready to describe how it works, and different ways that they can fix this problem.


The team's research paper will appear this week at the 2018 Conference on Programming Language Design and Implementation in Philadelphia.

Reporter

Jane Horrell

Jane Horrell
Department of Electrical and Electronic Engineering

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Contact details

Tel: +44 (0)20 7594 6263
Email: j.horrell@imperial.ac.uk

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