Abstract: As the size of semiconductor devices reduces to below 10 nm, quantum tunnelling and confinement of electrons, and single-electron charging effects associated with the discrete nature of charge, become increasingly significant. At the sub-10 nm scale, these effects can occur even at room temperature, raising the possibility of a quantum-effect ‘beyond-CMOS’ semiconductor device technology. At present, even in nominally classical CMOS FinFETs, at state-of-the-art channel thickness <10 nm, large threshold voltage variations associated with quantum confinement effects have been reported. For a ‘beyond CMOS technology, there is great potential in extending electronic materials from Si to layered materials such as graphene and MoS2. However, the controllable fabrication of electronic devices at the few nanometer scale is difficult by conventional means. In this regard, developments in advanced lithography such as pattern dependent electron beam lithography (EBL) and scanning probe lithography (SPL) are of great promise.
Silicon single-electron transistors (SETs) with sub-10 nm island size, capable of room-temperature (RT) operation, provide a means to transition smoothly from conventional nanoscale FETs to quantum-effect ‘beyond CMOS’ devices. In this talk, we present the fabrication and electrical characterisation of Si nanowire (NW) and point-contact SETs with island sizes of ~5 nm or less, capable of strong room-temperature operation. These devices can be defined by techniques such as a combination of electron beam lithography and oxidation, where pattern geometry is significant to reach the ~5 nm scale. Alternative methods such as focused ion beam gallium implantation and subsequent wet etching, and SPL, will also be discussed. The devices can be based on Si NWs of various lengths and these may be suspended or non-suspended, where the later case also allows investigation of the physics of electron-phonon interactions in 5 nm Si nanocrystals.