Abstract:
This talk presents a new approach to debugging High-level Synthesis (HLS) produced circuits. Our method allows a user with no detailed knowledge of the underlying hardware to debug in the context of the source code, while running the circuit in-situ. This is accomplished by automatically inserting debug instrumentation to trace the control and data flow in real-time. Our tracing architecture uses information from within the HLS process to dynamically select which signals are relevant to record cycle-by-cycle. A debugger application connects to the FPGA to retrieve this data and replay the execution in the context of the original source code, providing the user with a software-like debug environment with single-stepping, variable inspection and breakpoints. We will present several methods of optimizing the trace buffer usage, and show that we can replay over 3000 lines of source code per 100Kb of trace memory, a 23 times improvement over conventional tracing techniques. This work enables efficient real-time debugging of HLS circuits using a software-like debug interface, removing a major roadblock of HLS adoption.
Bio:
Steve Wilton is Professor in the Department of Electrical and Computer Engineering at University of British Columbia. He is part of the UBC SoC Research Group and a member of the Institute for Computing, Information, and Cognitive Systems (ICICS) and a Professional Engineer in the province of British Columbia. His research is in the areas of Computer Architecture and VLSI design, and is interested in architectures of next-generation Field-Programmable Gate Arrays and Computer-Aided Design algorithms that map circuits to these devices.