Cadence

 

Speaker

Dr Theo Drane

Abstract

A crucial component of Cadence’s logic synthesis solution Genus is that that focuses on the synthesis of arithmetic operators. The synthesis of a cluster of the fundamental operators that is power efficient, small, fast and can be successfully placed and routed is the persistent challenge and drives innovation.

Genus also provides a library of IP components, ChipWare, for all the essential chip building blocks (floating-point operations, transcendental functions, FIF Os, arbiters…). These are highly parameterisable, have to be functionally correct and highly optimised. Simulation based verification techniques are powerless in providing any real functional confidence for such components. Formal techniques are thus the main focus of ChipWare verification.

But we don’t just learn to get it right, we also learn how to get it wrong. Certain applications (DSP, vision processing, GPU ) are error tolerant. This freedom could be used to provide hardware improvements by using ideas from approximate computing. We also explore higher level synthesis for various number formats and the error analysis associated with ChipWare usage, particularly floating-point.

This talk will hint and meander through the myriad of associated research challenges. The landscape that Genus operates in draws us into close collaboration with other Cadence divisions (Logical Equivalence Checking – Conformal LEC , Model Checking – Jasper and High Level Synthesis – Stratus) as well as customers from the entire application space (GPU, CPU , DSP…).

Speaker Bio

Dr. Theo Drane started his career working for the Datapath consultancy Arithmatica in 2002 after completely a Mathematics degree from the University of Cambridge. He moved to Imagination Technologies in 2005 where his interests were datapath optimisation, verification and validation. After a two year sabbatical to work for an independent financial data provider, Markit, he returned to Imagination to head up their Datapath group while studying for a PhD in conjunction with Imperial College London’s Electrical and Electronic Engineering Department. He now leads the architectural optimization group for the Genus Synthesis solution in Cadence Design Systems, whose R&D is Cambridge, San Jose & Noida.