60036

Compilers

Module aims

Through this module you will understand the foundations, capabilities and limitations of optimising and parallelising compilers, as well as gain experience of the architectural challenges in compilers - the design of multi-layered intermediate representations to do the right optimisation at the right level. You will also learn how to build optimising compilers for domain-specific languages and domain-specific hardware, and discover the opportunities for co-designing the language, the compiler and the hardware, both in domain-specific and general-purpose computing contexts.    

Learning outcomes

Upon successful completion of this module, you will be able to:

* Make sound and defensible design decisions informed by understanding of what compilers can do and where compilers struggle.
* Identify suitable intermediate representations at different abstraction levels, leading to a compiler architecture based on  progressive lowering, recognising the importance of doing the right optimisation at the right level of representation.
* Develop novel compiler passes to support domain-specific language constructs.
* Develop novel compiler passes to support novel instruction set features and hardware structures, including FPGAs, spatial and reconfigurable accelerator architectures.
* Develop novel compiler passes to implement optimisation strategies for sequential and parallelisable code.
* Identify opportunities for co-design of processor hardware architecture and compiler mechanisms.    

Module syllabus

This module covers the following topics:
* Design of multi-level intermediate representations
* Register allocation using graph colouring and live-variable analysis
* Loop-invariant code motion using dataflow analysis
* Static single-assignment (SSA) form
* Loop-carried dependence and automatic parallelisation; loop-nest optimisations and tiling for data-locality improvement
* Code synthesis for linear algebra and tensor code using multi-level intermediate representations
* Code generation and optimisation for spatial architectures, such as FPGAs, CGRAs and dataflow.

Teaching methods

The module aims to build your understanding through interactive classes, driven by exposure to principles, examples in various programming languages and open-source compilers.  

We will introduce interesting ideas, and provocative challenges, signposting research directions and industrial relevance.

You will develop and test your understanding through unassessed, formative tutorial exercises, aiming to help prepare for exam questions.  

You will gain, hands-on experience using industry-standard tools and intermediate representations, via two practical assessed coursework exercises running concurrently with the lecture material.

An online service will be used as a discussion forum for the module. 

Assessments

The two practical coursework exercises will together contribute 20% of the mark for the module. There will be a final written exam, which counts for the remaining 80% of the marks.  
            
There will be detailed feedback on the coursework exercises which will include written feedback on your individual submission and in-class feedback explaining common pitfalls and suggestions for improvement.

Module leaders

Dr Hongxiang Fan
Professor Paul Kelly