In this section
@inproceedings{Millar:2025:10.1145/3680207.3765264,
author = {Millar, J and Huang, Y and Sethi, S and Haddadi, H and Madhavapeddy, A},
doi = {10.1145/3680207.3765264},
pages = {1060--1074},
title = {Benchmarking Ultra-Low-Power μNPUs},
url = {http://dx.doi.org/10.1145/3680207.3765264},
year = {2025}
}
TY - CPAPER
AB - Efficient on-device neural network (NN) inference offers predictable latency, improved privacy and reliability, and lower operating costs for vendors than cloud-based inference. This has sparked recent development of microcontroller-scale NN accelerators, also known as neural processing units (μNPUs), designed specifically for ultra-low-power applications. We present the first comparative evaluation of a number of commercially-available μNPUs, including the first independent benchmarks for multiple platforms. To ensure fairness, we develop and open-source a model compilation pipeline supporting consistent benchmarking of quantized models across diverse microcontroller hardware. Our resulting analysis uncovers both expected performance trends as well as surprising disparities between hardware specifications and actual performance, including certain μNPUs exhibiting unexpected scaling behaviors with model complexity. This work provides a foundation for ongoing evaluation of μNPU platforms, alongside offering practical insights for both hardware and software developers in this rapidly evolving space.
AU - Millar,J
AU - Huang,Y
AU - Sethi,S
AU - Haddadi,H
AU - Madhavapeddy,A
DO - 10.1145/3680207.3765264
EP - 1074
PY - 2025///
SP - 1060
TI - Benchmarking Ultra-Low-Power μNPUs
UR - http://dx.doi.org/10.1145/3680207.3765264
ER -
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